How to use variable delay in property?

I want to compare input bit with output bit using property but there is some delay between input and output. Let's say delay between input and output is 2 clock ticks.
So we can write SV property as below :
-----------------------------------------------------------------------
property bit_check(data_in,data_out);
bit x ;
(`true,x=data_in) |-> ##2 (data_out == x);
endproperty
-----------------------------------------------------------------------
But in my case the delay between input and output is not fix from beginning. I can get this information during the run time. So I should write property like following way :
-----------------------------------------------------------------------
property bit_check(data_in,data_out,delay);
bit x ;
(`true,x=data_in) |-> ##(delay) (data_out == x);
endproperty
-----------------------------------------------------------------------
When I use property like above the tool gives error as variable delay does not allow in property. It should be constant and the value should be predefined otherwise tool generates compilation error.
So to handle variable delay, I have added one more sequence between input and output instead of ##(delay). I wrote property like below and it works for me.
-----------------------------------------------------------------------
property bit_check(data_in,data_out,delay);
bit x ;
int cnt ;
(`true,x=data_in,cnt=0) |-> ((cnt < delay),cnt++)[*0:$] ##1 (cnt == delay) |-> (data_out == x);
endproperty

Insight on system verilog

(1) What is the difference between byte and bit [7:0]?Ans:-
byte is signed whereas bit [7:0] is unsigned.
(2)What is $root?
 Ans:-
$root refers to the top level instance in SystemVerilog
(3) What is the use of $cast?Ans:-
Typecasting in SV can be done either via static casting (', ', ') or dynamic casting via $cast task/function. $cast is very similar to dynamic_cast of C++. It checks whether the casting is possible or not in run-time and errors-out if casting is not possible.

(4) What is $unit?
Ans:-
bit b
task mytask;
b = 5 + $unit::b // b outside this task
endtask

(5) What's the difference between data type logic, reg and wire?

Data Type	Wire	Reg	Logic
Assignments	Continuous assignments	blocking/non blocking assignment	Both continuous assignment or blocking/non blocking assignment
Limitation	Wire, cannot hold data	Storage element, store data until next assignment

(6) What are the ways to avoid race condition between testbench and RTL using SystemVerilog?
There are mainly following ways to avoid the race condition between testbench and RTL using system verilog
1. Program Block
2. Clocking Block
3. Using non blocking assignments.

(7) What is Callback?
Callback in system verilog or verification : Callback is mechanism of changing to behavior of a verification component such as driver or generator or monitor without actually changing to code of the component.
It's used for functional coverage, inject error and in a scoreboard.

(8) What is "factory pattern" concept?
The term factory method is often used to refer to any method whose main purpose is creation of objects