Insight on system verilog

(1) What is the difference between byte and bit [7:0]?Ans:-
byte is signed whereas bit [7:0] is unsigned.
(2)What is $root?
 Ans:-
$root refers to the top level instance in SystemVerilog
(3) What is the use of $cast?Ans:-
Typecasting in SV can be done either via static casting (', ', ') or dynamic casting via $cast task/function. $cast is very similar to dynamic_cast of C++. It checks whether the casting is possible or not in run-time and errors-out if casting is not possible.

(4) What is $unit?
Ans:-
bit b
task mytask;
b = 5 + $unit::b // b outside this task
endtask

(5) What's the difference between data type logic, reg and wire?

Data Type	Wire	Reg	Logic
Assignments	Continuous assignments	blocking/non blocking assignment	Both continuous assignment or blocking/non blocking assignment
Limitation	Wire, cannot hold data	Storage element, store data until next assignment

(6) What are the ways to avoid race condition between testbench and RTL using SystemVerilog?
There are mainly following ways to avoid the race condition between testbench and RTL using system verilog
1. Program Block
2. Clocking Block
3. Using non blocking assignments.

(7) What is Callback?
Callback in system verilog or verification : Callback is mechanism of changing to behavior of a verification component such as driver or generator or monitor without actually changing to code of the component.
It's used for functional coverage, inject error and in a scoreboard.

(8) What is "factory pattern" concept?
The term factory method is often used to refer to any method whose main purpose is creation of objects