Usage of Systemverilog Automatic and Static keyword

Below code will help us to understand the application of automatic and static keyword of SystemVerilog.

Simulator used to compile below code is ius_9.2s33.

////////////////////////////////////////////////////////////////////////
 Code that shows application of AUTOMATIC TASK
////////////////////////////////////////////////////////////////////////
class check_automatic;
task automatic read1;
int a;
int b;
  a +=1;
  b +=1;
  #2;
  $display($time,"read 1 : a = %d, b= %d",a,b);
endtask
task display ();
 fork
   read1;
   read1;
 join
endtask
endclass
module test;
  check_automatic check = new;

   initial begin
    #5 check.display;
   end
endmodule

 

//// OUTPUT///

                   7read 1 : a =           1, b=           1
                   7read 1 : a =           1, b=           1
ncsim: *W,RNQUIE: Simulation is complete.\

 

////////////////////////////////////////////////////////////////////////
 Code that shows application of STATIC TASK
////////////////////////////////////////////////////////////////////////

class check_automatic;
task static read1;
int a;
int b;
  a +=1;
  b +=1;
  #2;
  $display($time,"read 1 : a = %d, b= %d",a,b);
endtask
task display ();
 fork
   read1;
   read1;
 join
endtask
endclass
module test;
  check_automatic check = new;

   initial begin
    #5 check.display;
   end
endmodule

                   7read 1 : a =           2, b=           2
                   7read 1 : a =           2, b=           2
ncsim: *W,RNQUIE: Simulation is complete.