Usage of Systemverilog Automatic and Static keyword

Below code will help us to understand the application of automatic and static keyword of SystemVerilog.

Simulator used to compile below code is ius_9.2s33.

////////////////////////////////////////////////////////////////////////
 Code that shows application of AUTOMATIC TASK
////////////////////////////////////////////////////////////////////////
class check_automatic;
task automatic read1;
int a;
int b;
  a +=1;
  b +=1;
  #2;
  $display($time,"read 1 : a = %d, b= %d",a,b);
endtask
task display ();
 fork
   read1;
   read1;
 join
endtask
endclass
module test;
  check_automatic check = new;

   initial begin
    #5 check.display;
   end
endmodule

 

//// OUTPUT///

                   7read 1 : a =           1, b=           1
                   7read 1 : a =           1, b=           1
ncsim: *W,RNQUIE: Simulation is complete.\

 

////////////////////////////////////////////////////////////////////////
 Code that shows application of STATIC TASK
////////////////////////////////////////////////////////////////////////

class check_automatic;
task static read1;
int a;
int b;
  a +=1;
  b +=1;
  #2;
  $display($time,"read 1 : a = %d, b= %d",a,b);
endtask
task display ();
 fork
   read1;
   read1;
 join
endtask
endclass
module test;
  check_automatic check = new;

   initial begin
    #5 check.display;
   end
endmodule

                   7read 1 : a =           2, b=           2
                   7read 1 : a =           2, b=           2
ncsim: *W,RNQUIE: Simulation is complete.

Elaboration and Simulation Phases of UVM and OVM

OVM Phases :

The OVM provides the following predefined phases for all ovm_components.

•  build
• connect
• end_of_elaboration
• start_of_simulation
• run
• extract
• check
• report

UVM Phases :

1. new() ------------------------------ The constructor
2. build_phase() --------------------- Create components using new or the factory
3. connect_phase() ----------------- Make port, export and implementation connections
4. end_of_elaboration_phase() ---- After all connections have been hardened
5. start_of_simulation_phase() ---- Just before simulation starts
6. run_phase() ----------------------- Runs simulation
7. extract_phase() ------------------ Post-processing 1
8. check_phase() ------------------- Post-processing 2
9. report_phase() ------------------- Post-processing 3
10. final_phase() --------------------- Backstop 

Are OVM & UVM Macros Evil? A Cost-Benefit Analysis

http://verificationhorizons.verificationacademy.com/volume-7_issue-2/articles/stream/are-ovm-and-uvm-macros-evil-a-cost-benefit-analysis_vh-v7-i2.pdf

How to use variable delay in property?

I want to compare input bit with output bit using property but there is some delay between input and output. Let's say delay between input and output is 2 clock ticks.
So we can write SV property as below :
-----------------------------------------------------------------------
property bit_check(data_in,data_out);
bit x ;
(`true,x=data_in) |-> ##2 (data_out == x);
endproperty
-----------------------------------------------------------------------
But in my case the delay between input and output is not fix from beginning. I can get this information during the run time. So I should write property like following way :
-----------------------------------------------------------------------
property bit_check(data_in,data_out,delay);
bit x ;
(`true,x=data_in) |-> ##(delay) (data_out == x);
endproperty
-----------------------------------------------------------------------
When I use property like above the tool gives error as variable delay does not allow in property. It should be constant and the value should be predefined otherwise tool generates compilation error.
So to handle variable delay, I have added one more sequence between input and output instead of ##(delay). I wrote property like below and it works for me.
-----------------------------------------------------------------------
property bit_check(data_in,data_out,delay);
bit x ;
int cnt ;
(`true,x=data_in,cnt=0) |-> ((cnt < delay),cnt++)[*0:$] ##1 (cnt == delay) |-> (data_out == x);
endproperty

Insight on system verilog

(1) What is the difference between byte and bit [7:0]?Ans:-
byte is signed whereas bit [7:0] is unsigned.
(2)What is $root?
 Ans:-
$root refers to the top level instance in SystemVerilog
(3) What is the use of $cast?Ans:-
Typecasting in SV can be done either via static casting (', ', ') or dynamic casting via $cast task/function. $cast is very similar to dynamic_cast of C++. It checks whether the casting is possible or not in run-time and errors-out if casting is not possible.

(4) What is $unit?
Ans:-
bit b
task mytask;
b = 5 + $unit::b // b outside this task
endtask

(5) What's the difference between data type logic, reg and wire?

Data Type	Wire	Reg	Logic
Assignments	Continuous assignments	blocking/non blocking assignment	Both continuous assignment or blocking/non blocking assignment
Limitation	Wire, cannot hold data	Storage element, store data until next assignment

(6) What are the ways to avoid race condition between testbench and RTL using SystemVerilog?
There are mainly following ways to avoid the race condition between testbench and RTL using system verilog
1. Program Block
2. Clocking Block
3. Using non blocking assignments.

(7) What is Callback?
Callback in system verilog or verification : Callback is mechanism of changing to behavior of a verification component such as driver or generator or monitor without actually changing to code of the component.
It's used for functional coverage, inject error and in a scoreboard.

(8) What is "factory pattern" concept?
The term factory method is often used to refer to any method whose main purpose is creation of objects

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13. Recommend other businesses that might benefit your customers.
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15. Empower your customer service staff to solve all possible issues.
16. Be cheerful and polite.
17. Easy customer communications over multiple channels.
18. Feature customers and/or customer stories in a blog post or other social media.
19. Include customer input in new product development.
20. Unsubscribing from your newsletters should be easy as subscribing.
21. Accept customer ratings and reviews of your product.
22. Have a large enough staff to handle customer issues in a timely manner.
23. No hidden fees or agendas.
24. Easy product returns/exchanges.
25. Allow customers to get to know your employees

Difference between Pcie gen2 and gen3

Hot protocols

• AMBA 4
• AMBA AHB
• AMBA AXI
• AMBA APB
• CAN
• Ethernet
• HDMI
• I2C
• JTAG
• LIN
• MIPI CSI-2
• MIPI DSI
• MIPI M-PHY
• MIPI SLIMbus
• MIPI UniPro
• MIPI DigRF v4
• OCP
• PCI Express
• PCI
• PLB
• SAS
• Serial ATA (SATA)
• Serial Rapid IO
• USB (with OTG)
• USB SuperSpeed
• UART
• JPEG
• Mobile Storage
• XAUI

Hot memories

DDR2

DDR3

DDR4

DDR4 SDRAM

DDR NVM

EEPROM

Flash ONFI 3.0

Flash PPM

Flash Toggle2NAND

GDDR3

GDDR4

GDDR5

LBA NAND

LPDDR2

LRDIMM

MMC 4.41

One NAND

QDR SRA

SD/SDIO 2.0

SD/SDIO 3.0

SDRAM

SRAM

SRAM cellular

Toggle NAND

Wide I/O SDRAM

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Useful Links for Verification Engg.

Places To Go

• UVM World
• Specman Verification
• Cool Verification
• DigitalVerification Blog
• EDA Cafe
• Team Specman
• VMM Central
• Verification Martial Arts
• Verification Guild
• OVM World
• Trusster
• SysWip
• DVT Eclipse
• Verification Academy